スポンサーリンク
Renesas Electronics Corp. | 論文
- A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
- A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(VLSI Design and CAD Algorithms)
- A Small-Chip-Area Transceiver IC for Bluetooth Featuring a Digital Channel-Selection Filter(Analog Circuit and Device Technologies)
- A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors(Low-Power System LSI, IP and Related Technologies)
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- Development of an Enterprise-Wide Yield Management System Using Critical Area Analysis for High-Product-Mix Semiconductor Manufacturing
- Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture(Novel Device Architectures and System Integration Technologies)
- Selective-Sets Resizable Cache Memory Design for High-Performance and Low-Power CPU Core(Low-Power System LSI, IP and Related Technologies)
- Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs(Test)(VLSI Design and CAD Algorithms)
- A Low-Power Microcontroller with Body-Tied SOI Technology(Low-Power System LSI, IP and Related Technologies)
- 1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver
- A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop( Analog Circuit Techniques and Related Topics)
- Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
- Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
- A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design(Novel Device Architectures and System Integration Technologies)
- Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use(Analog Circuit and Device Technologies)
- A Quaternary Decision Diagram Machine : Optimization of Its Code
- Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS(Digital,Low-Power, High-Speed LSIs and Related Technologies)
スポンサーリンク