Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture(<Special Section>Novel Device Architectures and System Integration Technologies)

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概要

• 論文の詳細を見る

• This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200MHz clock frequency and 250mW power dissipation. In addition, 1M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1mm^2 in 90nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.

• 社団法人電子情報通信学会の論文
• 2006-11-01

著者

• Nakajima Masami

  Renesas Technology Corp.

• SHIMIZU Toru

  Renesas Technology Corp.

• KAINAGA Masahiro

  Renesas Technology Corp.

• Shimizu Toru

  Renesas Electronics Corp.

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