A Quaternary Decision Diagram Machine : Optimization of Its Code

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概要

• 論文の詳細を見る

• This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.

• 2010-08-01

著者

• SASAO Tsutomu

  Department of Computer Science and Electronics, Kyushu Institute of Technology

• BUTLER Jon

  海軍大学院大学

• Butler Jon

  Naval Postgraduate School Ca Usa

• NAKAHARA Hiroki

  Department of Computer Science and Electronics, Kyushu Institute of Technology

• MATSUURA Munehiro

  Department of Computer Science and Electronics, Kyushu Institute of Technology

• KAWAMURA Yoshifumi

  Renesas Technology Corp.

• Sasao T

  Department Of Computer Science And Electronics Kyushu Institute Of Technology

• Sasao Tsutomu

  Kyushu Inst. Of Technol. Iizuka‐shi Jpn

• Butler Jon

  Naval Postgraduate School

• Nakahara Hiroki

  Kyushu Institute Of Technology

• Kawamura Yoshifumi

  Renesas Electronics Corp.

• MATSUURA Munehiro

  Kyushu Institute of Technology

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