Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes programmable architectures and design methods for numeric function generators (NFGs) of two-variable functions. To realize a two-variable function in hardware, we partition a given domain of the function into segments, and approximate the function by a polynomial in each segment. This paper introduces two planar segmentation algorithms that efficiently partition a domain of a two-variable function. This paper also introduces a design method for symmetric two-variable functions (i.e. f(X, Y)=f(Y, X)). This method can reduce the memory size needed for symmetric functions by nearly half with small speed penalty. The proposed architectures allow a systematic design of various two-variable functions. We compare our approach with one based on a one-variable NFG. FPGA implementation results show that, for a complicated function, our NFG achieves 57% of memory size and 60% of delay time of a circuit designed based on a one-variable NFG.

• Information and Media Technologies 編集運営会議の論文

著者

• Sasao Tsutomu

  Kyushu Inst. Of Technol. Iizuka‐shi Jpn

• T. Butler

  Naval Postgraduate School

• Nagayama Shinobu

  Hiroshima City University

関連論文

• Compact Numerical Function Generators Based on Quadratic Approximation : Architecture and Synthesis Method(Circuit Synthesis,VLSI Design and CAD Algorithms)
• Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs(Logic Synthesis and Verification,VLSI Design and CAD Algorithms)
• Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs(Logic Synthesis, VLSI Design and CAD Algorithms)
• Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams (Special Issue on Multiple-Valued Logic)
• A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams
• A Quaternary Decision Diagram Machine : Optimization of Its Code
• A Memory-Based Programmable Logic Device Using a Look-Up Table Cascade with Synchronous SRAMs
• A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories
• Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators
• Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators
• Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators

もっと見る 閉じる

スポンサーリンク