A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edge-valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function ƒ by the values of l and p for which ƒ is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of ƒ and p is a measure of the rate at which ƒ increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p = 1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs.

• （社）電子情報通信学会の論文
• 2010-08-01

著者

• NAGAYAMA Shinobu

  Department of Computer and Network Engineering, Hiroshima City University

• SASAO Tsutomu

  Department of Computer Science and Electronics, Kyushu Institute of Technology

• BUTLER Jon

  Department of Electrical and Computer Engineering, Naval Postgraduate School

• Butler Jon

  Department Of Electrical And Computer Engineering Naval Postgraduate School

• Sasao Tsutomu

  Kyushu Inst. Of Technol. Iizuka‐shi Jpn

• Sasao Tsutomu

  Department Of Computer Science And Electronics Kyushu Institute Of Technology

• Nagayama Shinobu

  Department Of Computer And Network Engineering Hiroshima City University

関連論文

• A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams
• Compact Numerical Function Generators Based on Quadratic Approximation : Architecture and Synthesis Method(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
• Bi-Partition of Shared Binary Decision Diagrams(Special Section on VLSI Design and CAD Algorithms)
• Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams (Special Issue on Multiple-Valued Logic and Its Applications)
• Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs(Logic Synthesis and Verification,VLSI Design and CAD Algorithms)
• Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs(Logic Synthesis, VLSI Design and CAD Algorithms)
• A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks(Discrete Mathematics and Its Applications)
• Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams (Special Issue on Multiple-Valued Logic)
• BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades(Logic Synthesis and Verification,VLSI Design and CAD Algorithms)
• A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams
• A Quaternary Decision Diagram Machine : Optimization of Its Code
• Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries(Logic Synthesis,VLSI Design and CAD Algorithms)
• A Parallel Branching Program Machine for Sequential Circuits : Implementation and Evaluation
• A Memory-Based Programmable Logic Device Using a Look-Up Table Cascade with Synchronous SRAMs
• A Realization of Multiple-Output Functions by a Look-Up Table Ring(Logic Synthesis)(VLSI Design and CAD Algorithms)
• Design Methods of Radix Converters Using Arithmetic Decompositions(Computer Components)
• A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA(Computer Components)
• Area-Time Complexities of Multi-Valued Decision Diagrams(Discrete Mathematics and Its Applications)
• On Properties of Kleene TDDs(Special Issue on Test and Diagnosis of VLSI)
• Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions (Special Section on VLSI Design and CAD Algorithms)
• Compact Representations of Logic Functions Using Heterogeneous MDDs(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
• A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator(Simulation and Verification,VLSI Design and CAD Algorithms)
• A Design Algorithm for Sequential Circuits Using LUT Rings(Logic Synthesis, VLSI Design and CAD Algorithms)
• Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form(Logic Synthesis)(VLSI Design and CAD Algorithms)
• Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders(Digital Circuits and Computer Arithmetic, Recent Advances in Circuits and Systems-Part 1)
• A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton
• A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories
• Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators
• Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators
• A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition
• On the Numbers of Products in Prefix SOPs for Interval Functions
• Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators
• On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems

もっと見る 閉じる

スポンサーリンク