A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
スポンサーリンク
概要
- 論文の詳細を見る
The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We realized many benchmark functions on the PBM128, and compared its memory size, computation time, and power consumption with the Intels Core2Duo microprocessor. The PBM128 requires approximately a quarter of the memory for the Core2Duo, and is 21.4-96.1 times faster than the Core2Duo. It dissipates a quarter of the power of the Core2Duo. Also, we realized packet filters such as an access controller and a firewall, and compared their performance with software on the Core2Duo. For these packet filters, the PBM128 requires approximately 17% of the memory for the Core2Duo, and is 21.3-23.7 times faster than the Core2Duo.
著者
-
SASAO Tsutomu
Department of Computer Science and Electronics, Kyushu Institute of Technology
-
NAKAHARA Hiroki
Department of Computer Science and Electronics, Kyushu Institute of Technology
-
MATSUURA Munehiro
Department of Computer Science and Electronics, Kyushu Institute of Technology
-
KAWAMURA Yoshifumi
Renesas Technology Corp.
関連論文
- A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams
- Compact Numerical Function Generators Based on Quadratic Approximation : Architecture and Synthesis Method(Circuit Synthesis,VLSI Design and CAD Algorithms)
- A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
- Bi-Partition of Shared Binary Decision Diagrams(Special Section on VLSI Design and CAD Algorithms)
- Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams (Special Issue on Multiple-Valued Logic and Its Applications)
- Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs(Logic Synthesis and Verification,VLSI Design and CAD Algorithms)
- Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs(Logic Synthesis, VLSI Design and CAD Algorithms)
- A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks(Discrete Mathematics and Its Applications)
- BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades(Logic Synthesis and Verification,VLSI Design and CAD Algorithms)
- A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams