A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator(Simulation and Verification,<Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evaluates the given circuit stored in the memory. The LUT cascade emulator runs on an ordinary PC. This paper also compares the method with a Levelized Compiled Code (LCC) simulator and a simulator using a Quasi-Reduced Multi-valued Decision Diagram (QRMDD). Our simulator is 3.5 to 10.6 times faster than the LCC, and 1.1 to 3.9 times faster than the one using a QRMDD. The simulation setup time is 2.0 to 9.8 times shorter than the LCC. The necessary amount of memory is 1/1.8 to 1/5.5 of the one using a QRMDD.
- 社団法人電子情報通信学会の論文
- 2006-12-01
著者
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SASAO Tsutomu
Department of Computer Science and Electronics, Kyushu Institute of Technology
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NAKAHARA Hiroki
Department of Computer Science and Electronics, Kyushu Institute of Technology
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MATSUURA Munehiro
Department of Computer Science and Electronics, Kyushu Institute of Technology
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Sasao T
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Sasao Tsutomu
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Nakahara Hiroki
Kyushu Institute Of Technology
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MATSUURA Munehiro
Kyushu Institute of Technology
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Matsuura Munehiro
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Nakahara Hiroki
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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