Compact Representations of Logic Functions Using Heterogeneous MDDs(Logic and High Synthesis)(<Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
In this paper, we propose a compact representation of logic functions using Multi-valued Decision Diagrams (MDDs) called heterogeneous MDDs. In a heterogeneous MDD, each variable may take a different domain. By partitioning binary input variables and representing each partition as a single multi-valued variable, we can produce a heterogeneous MDD with 16% smaller memory size than a Reduced Ordered Binary Decision Diagram (ROBDD), and with comparable memory size to Free Binary Decision Diagrams (FBDDs). And also, heterogeneous MDDs have shorter Average Path Length (APL) than ROBDDs and FBDDs. We minimized a large number of benchmark functions to show the compactness of heterogeneous MDDs.
- 社団法人電子情報通信学会の論文
- 2003-12-01
著者
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Sasao Tsutomu
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Sasao Tsutomu
Department Of Computer Science And Electronics Kyushu Institute Of Technology:center For Microelectr
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Nagayama Shinobu
Department Of Computer And Network Engineering Hiroshima City University
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Nagayama Shinobu
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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