Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form(Logic Synthesis)(<Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
Checking the equivalence of two Boolean functions under permutation of the variables is an important problem in the synthesis of multiplexer-based field-programmable gate arrays (FPGAs), and the problem is known as Boolean matching. This paper presents an efficient breadth-first search technique for computing a canonical form-namely P-representative-of Boolean functions under permutation of the variables. Two functions match if they have the same P-representative. On an ordinary workstation, on the average, the method requires several microseconds to check the Boolean matching of functions with up to eight variables against a library with tens of thousands of cells.
- 社団法人電子情報通信学会の論文
- 2004-12-01
著者
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Debnath Debatosh
Department Of Computer Science And Engineering Oakland University
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Sasao Tsutomu
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Sasao Tsutomu
Department Of Computer Science And Electronics Kyushu Institute Of Technology And Engineering Oaklan
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Debnath Debatosh
Department Of Computer Science And Electronics Faculty Of Computer Science And Systems Engineering K
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DEBNATH Debatosh
Department of Computer Science and Engineering, Oakland University
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