A Design Algorithm for Sequential Circuits Using LUT Rings(Logic Synthesis, <Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps : The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits : the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.
- 社団法人電子情報通信学会の論文
- 2005-12-01
著者
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SASAO Tsutomu
Department of Computer Science and Electronics, Kyushu Institute of Technology
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NAKAHARA Hiroki
Department of Computer Science and Electronics, Kyushu Institute of Technology
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MATSUURA Munehiro
Department of Computer Science and Electronics, Kyushu Institute of Technology
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Sasao T
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Sasao Tsutomu
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Nakahara Hiroki
Kyushu Institute Of Technology
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MATSUURA Munehiro
Kyushu Institute of Technology
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Matsuura Munehiro
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Nakahara Hiroki
Department Of Computer Science And Electronics Kyushu Institute Of Technology
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