Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs(Logic Synthesis and Verification,<Special Section>VLSI Design and CAD Algorithms)

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概要

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• Numerical function generators (NFGs) realize arithmetic functions, such as e^x, sin(πx), and √<x>, in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.

• 2007-12-01

著者

• NAGAYAMA Shinobu

  Department of Computer and Network Engineering, Hiroshima City University

• SASAO Tsutomu

  Department of Computer Science and Electronics, Kyushu Institute of Technology

• BUTLER Jon

  Department of Electrical and Computer Engineering, Naval Postgraduate School

• Butler Jon

  Department Of Electrical And Computer Engineering Naval Postgraduate School

• Sasao Tsutomu

  Kyushu Inst. Of Technol. Iizuka‐shi Jpn

• Sasao Tsutomu

  Department Of Computer Science And Electronics Kyushu Institute Of Technology

• Nagayama Shinobu

  Department Of Computer And Network Engineering Hiroshima City University

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