A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories
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概要
- 論文の詳細を見る
A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2006-04-30
著者
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Sasao Tsutomu
Kyushu Inst. Of Technol. Iizuka‐shi Jpn
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Nakahara Hiroki
Kyushu Institute Of Technology
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MATSUURA Munehiro
Kyushu Institute of Technology
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NAKAMURA Kazuyuki
Kyushu Institute of Technology
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TANAKA Katsumasa
Kyushu Institute of Technology
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YOSHIZUMI Kenichi
Kyushu Institute of Technology
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IGUCHI Yukihiro
Meiji University
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Nakamura Kazuyuki
Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japan
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Matsuura Munehiro
Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japan
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Iguchi Yukihiro
Meiji University, 1-1-1 Higashimita, Kawasaki 214-8571, Japan
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Sasao Tsutomu
Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japan
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