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Renesas Electronics Corp. | 論文
- A Parallel Branching Program Machine for Sequential Circuits : Implementation and Evaluation
- Reduction of Area per Good Die for SoC Memory Built-In Self-Test
- A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis
- A 45-nm 37.3GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
- Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
- Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme
- Design and Performance of Intergate-Channel-Connected Multi-Gate pHEMT for Antenna Switch
- Low Power Platform for Embedded Processor LSIs
- A Wide Dynamic Range Variable Gain Amplifier with Enhanced IP1 dB and Temperature Compensation
- Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
- Impact of Discrete-Charge-Induced Variability on Scaled MOS Devices
- Statistical p–n Junction Leakage Model via Trap Level Fluctuation for Refresh-Time-Oriented Dynamic Random Access Memory Design
- Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
- Impact of Discrete-Charge-Induced Variability on Scaled MOS Devices
- Development of Evaluation Method for Estimating Stress-Induced Change in Drain Current in Deep-sub-micron MOSFETs
- On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes
- Design Aid of Multi-core Embedded Systems with Energy Model