Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

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概要

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• Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.

著者

• Nakao Michinobu

  Renesas Technology Corp.

• Kaneko Shun'ichi

  Hokkaido University

• SAITO Yoshikazu

  Renesas Electronics Corp.

• Matsumoto Chizu

  Yokohama Research Laboratory, Hitachi, Ltd.

• Hamamura Yuichi

  Yokohama Research Laboratory, Hitachi, Ltd.

• Yamasaki Kaname

  Renesas Electronics Corp.

• NAKAO Michinobu

  Renesas Electronics Corp.

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• Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

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