A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop(<Special Section> Analog Circuit Techniques and Related Topics)
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概要
- 論文の詳細を見る
A false lock free delay-locked loop (DLL) achieving a wide frequency operation and a fine timing resolution is presented. A novel false lock detection technique is proposed to solve the trade-off between a wide frequency range and false locks. This technique enables a fine timing resolution even at a high frequency. In addition, the duty cycle of the input clock is not required to be 50%. This technique is applied to the DLLs in analog front-end LSIs of digital camera systems, with a range of 4〜65 MHz (×16) and a timing resolution of 9°(40 stages).
- 社団法人電子情報通信学会の論文
- 2006-02-01
著者
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MATSUURA Tatsuji
Renesas Technologies Co.
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IMAIZUMI Eiki
Renesas Technology Corp.
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AIBARA Yasutoshi
Renesas Technology Corp.
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TAKAGISHI Hiroaki
Renesas Technology Corp.
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Matsuura Tatsuji
Semiconductor Technology Academic Research Center (starc)
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Matsuura Tatsuji
Renesas Technology Corp.
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Matsuura Tatsuji
Renesas Electronics Corp.
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