605 デジタル画像相関法によるひずみ計測と有限要素解析による次世代三次元積層試作チップの信頼性評価(OS6-1 シリコン貫通ビア技術と強度信頼性)

概要

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The three-dimensional chip stacking IC (3D-SIC) technology is a new packing technology to realize high-density and high-speed transmission. In such high-density chip stacking technology, the reliability evaluation of structure is also an important issue. Although the fmite element method (FEM) is often used in a stress analysis of reliability evaluation of micro-structures, it is not easy to perform the accurate analyses because of the non-linear behavior of components in the complicated structure of the 3D-SIC. The accuracy of the FEM needed to be verified by experiments. Digital image correlation (DIC) is used to measure the strain distribution on the surface of the cross-section of a 3D-SIC test chip under the thermal stress, and it verified the accuracy of the FEM
一般社団法人日本機械学会の論文
2010-10-09