Design and Evaluation of a 54×54-bit Multiplier Based on Differential-Pair Circuitry(Digital,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)
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概要
- 論文の詳細を見る
This paper presents a high-speed 54×54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18μm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88ns with 74.2mW at 400MHz from a 1.8V supply occupying a 0.85mm^2 active area.
- 社団法人電子情報通信学会の論文
- 2007-04-01
著者
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HANYU Takahiro
Research Institute of Electrical Communication, Tohoku University
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HANYU Takahiro
RIEC, Tohoku University
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望月 明
Research Institute Of Electrical Communication Tohoku University
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Hanyu Takahiro
Riec Tohoku University
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Hanyu Takahiro
Research Institute Of Electrical Communication Tohoku University
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MOCHIZUKI Akira
Research Institute of Electrical Communication, Tohoku University
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SHIRAHAMA Hirokatsu
Research Institute of Electrical Communication, Tohoku University
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Shirahama Hirokatsu
Research Institute Of Electrical Communication Tohoku University
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Mochizuki Akira
The Research Institute Of Electrical Communication Tohoku University
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