HANYU Takahiro | Research Institute of Electrical Communication, Tohoku University

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概要

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著作論文

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving
Design and Evaluation of a 54×54-bit Multiplier Based on Differential-Pair Circuitry(Digital,Low-Power, High-Speed LSIs and Related Technologies)
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic(Novel Device Architectures and System Integration Technologies)
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI(Papers Selected from ITC-CSCC 2004)
Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer(New System Paradigms for Integrated Electronics)
Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling(New System Paradigms for Integrated Electronics)
Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control(Low-Power System LSI, IP and Related Technologies)
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic(Novel Device Architectures and System Integration Technologies)
Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links
Special Section on Novel Device Architectures and System Integration Technologies

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