Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic(<Special Section>Novel Device Architectures and System Integration Technologies)
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概要
- 論文の詳細を見る
A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18μm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.
- 社団法人電子情報通信学会の論文
- 2006-11-01
著者
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ONIZAWA Naoya
Research Institute of Electrical Communication, Tohoku University
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HANYU Takahiro
Research Institute of Electrical Communication, Tohoku University
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Onizawa Naoya
Research Institute Of Electrical Communication Tohoku University
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Onizawa Naoya
Tohoku Univ. Sendai‐shi Jpn
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Hanyu Takahiro
Research Institute Of Electrical Communication Tohoku University
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