Performance and cost evaluations of on-chip network topologies in FPGAs (リコンフィギャラブルシステム)

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概要

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• The on-chip interconnection network has been used to connect many modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance and cost of the system, and various network topologies have been proposed so far. To reveal cost-efficient on-chip network structure in the reconfigurable systems, in this paper, we estimate the performance of 2-D mesh, 2-D torus, fat trees, Spidergon, and Concentrated mesh by using a network simulator. Then these topologies are synthesized by using the Xilinx ISE in order to show the number of slices required for each topology. The evaluation results show that Concentrated mesh outperforms 2D-mesh in terms of performance and cost.

• 2009-05-07

著者

• IN Sen

  Department of Information and Computer Science, Keio University

• MATSUTANI Hiroki

  Department of Information and Computer Science, Keio University

• WANG Daihan

  Department of Information and Computer Science, Keio University

• KOIBUCHI Michihiro

  National Institute of Informatics

• AMANO Hideharu

  Department of Information and Computer Science, Keio University

• Amano Hideharu

  Keio Univ. Yokohama Jpn

• Matsutani Hiroki

  Keio Univ. Yokohama Jpn

• Matsutani Hiroki

  Graduate School Of Science And Technology Keio University

• In Sen

  Department Of Information And Computer Science Keio University

• Wang Daihan

  Department Of Information And Computer Science Keio University

• AMANO Hideharu

  Faculty of Science and Technology, Keio University

• Amano Hideharu

  Faculty Of Science And Technology Keio University

• Amano Hideharu

  Department Of Computer Science Keio University

• Amano Hideharu

  Department Of Computer Science Graduate School Of Keio University

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