Performance Evaluation of Instruction Set Architecture of MBP-Light in JUMP-1(<Special Issue> Development of Advanced Computer Systems)

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概要

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• The instruction set architecture of MBP-light, a dedicated processor for the DSM (Distributed Shared Memory) management of JUMP-1 is analyzed with a real prototype The Buffer-Register Architecture proposed for MBP-core improves performance with 5.64% in the home cluster and 6.27% in a remote cluster Only a special instruction for hashing cluster address is efficient and improves the performance with 2.80%, but other special instructions aie almost useless. It appears that the dominant operations in the DSM management program were handling packet queues assigned into the local cluster Thus, common RISC instructions, especially load/store instructions, are frequently used. Separating instruction and data memory improves performance with 33% The results suggest that another alternative which provides separate on-chip cache and instructions dedicated for packet queue management is advantageous.

• 2003-10-01

著者

• Amano Hideharu

  Department Of Computer Science Graduate School Of Keio University

• SUZUKI Nariaki

  Department of Computer Science, Keio University

• Suzuki Nariaki

  Department Of Computer Science Keio University

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