Evaluation of a multicore reconfigurable architecture (VLSI設計技術)

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概要

• 論文の詳細を見る

• A multicore reconfigurable architecture consisting of multiple small computational cores connected by an interconnection network is introduced. A comparision of a tile-based architecture and the proposed multicore architecture in terms of performance is examined. Then, an evaluation with different core sizes is implemented in order to find out how the size of cores in a homogeneous system influences on the performance and the internal fragmentation of target applications. Using real applications implemented on the proposed architecture in which cores are based on NEC Electronics' DRP-1, the evaluation result shows that the size of core is a trade-off between throughput and resource usage, and the size of two or three DRP tiles is an appropriate choice for many cases.

• 社団法人電子情報通信学会の論文
• 2009-01-22

著者

• Amano Hideharu

  Keio Univ. Yokohama Jpn

• Amano Hideharu

  Graduate School Of Science And Technology Keio University

• Matsutani Hiroki

  Keio Univ. Yokohama Jpn

• Matsutani Hiroki

  Graduate School Of Science And Technology Keio University

• AMANO Hideharu

  Faculty of Science and Technology, Keio University

• Manh Tuan

  Graduate School Of Science And Technology Keio University

• KATSURA Naohiro

  Graduate School of Science and Technology, Keio University

• Katsura Naohiro

  Graduate School Of Science And Technology Keio University

• Matsutani Hiroki

  Graduate School of Information Science and Technology, The University of Tokyo

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