A Leakage Efficient Instruction TLB Design for Embedded Processors

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概要

• 論文の詳細を見る

• This paper presents a leakage-efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.

• （社）電子情報通信学会の論文
• 2011-08-01

著者

• Amano Hideharu

  Keio Univ. Yokohama Jpn

• IKEBUCHI Daisuke

  Faculty of Science and Technology, Keio University

• SUNATA Tetsuya

  Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology

• AMANO Hideharu

  Faculty of Science and Technology, Keio University

• ZHAO LEI

  慶大

• HUI XU

  慶大

• SUNATA TETSUYA

  東京農工大

• NAMIKI MITARO

  東京農工大

• Ikebuchi Daisuke

  Faculty Of Science And Technology Keio University

• LEI Zhao

  the Faculty of Science and Technology, Keio University

• XU Hui

  the Faculty of Science and Technology, Keio University

• IKEBUCHI Daisuke

  the Faculty of Science and Technology, Keio University

• SUNATA Tetsuya

  the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology

• NAMIKI Mitaro

  the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology

• AMANO Hideharu

  the Faculty of Science and Technology, Keio University

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• A Leakage Efficient Data TLB Design for Embedded Processors
• A Leakage Efficient Instruction TLB Design for Embedded Processors

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