Performance Evaluation of Instruction Set Architecture of MBP-light : a distributed memory controller for a large scale multiprocessor

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概要

• 論文の詳細を見る

• The instruction set architecture of MBP-light, a dedicated processor for the DSM (Distributed Shared Memory) management of JUMP-1 is analyzed with a real prototype. The Buffer-Register Architecture proposed for MBP-core improves performance with 5.64% in the home cluster and 6.27% in a remote cluster. It appears that the dominant operations in the DSM management program are handling packet queues assigned into the local cluster. Thus, common RISC instructions, especially load/store instructions, are frequently used. Separating instruction and data memory improves performance with 33%. The results suggest that another alternative which provides separate on-chip cache and instructions dedicated for packet queue management is advantageous.

• 一般社団法人情報処理学会の論文
• 2003-06-24

著者

• Suzuki Noriaki

  Department of Mathematics, Meijo University

• AMANO Hideharu

  Department of Information and Computer Science, Keio University

• Suzuki Noriaki

  Department Of Computer Science Graduate School Of Keio University

• Amano Hideharu

  Department Of Computer Science Graduate School Of Keio University

• SUZUKI NORIAKI

  Department of Chemical Engineering, Shizuoka University

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