A temporal correlation based port combination methodology for application-specific networks-on-chip on FPGAs (計算機アーキテクチャ・2007年並列/分散/協調処理に関する『旭川』サマー・ワークショップ(SWoPP旭川2007)--研究会・連続同時開催)

概要

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A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port com-bination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology, it does not affect the design of the other layers, such as task map-ping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the non-temporal correlation algorithm suffers from 30% performance loss.
一般社団法人情報処理学会の論文
2007-08-01