Matsutani Hiroki | Graduate School of Information Science and Technology, The University of Tokyo

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• 同名の論文著者
• Graduate School of Information Science and Technology, The University of Tokyoの論文著者

関連著者

• Matsutani Hiroki

  Graduate School of Information Science and Technology, The University of Tokyo

• Amano Hideharu

  Graduate School Of Science And Technology Keio University

• Amano Hideharu

  Keio Univ. Yokohama Jpn

• Matsutani Hiroki

  Keio Univ. Yokohama Jpn

• Matsutani Hiroki

  Graduate School Of Science And Technology Keio University

• AMANO Hideharu

  Faculty of Science and Technology, Keio University

• Manh Tuan

  Graduate School Of Science And Technology Keio University

• KATSURA Naohiro

  Graduate School of Science and Technology, Keio University

• Katsura Naohiro

  Graduate School Of Science And Technology Keio University

• Nakamura Hiroshi

  Graduate School Of Information Science And Technology The University Of Tokyo

• He Yuan

  Graduate School of Engineering, The University of Tokyo

• SASAKI Hiroshi

  Graduate School of Agricultural and Life Sciences, The University of Tokyo

• KOIBUCHI Michihiro

  National Institute of Informatics

• Wang Daihan

  Department Of Information And Computer Science Keio University

• Wang Daihan

  Graduate School of Science and Technology, Keio University

• Amano Hideharu

  Faculty Of Science And Technology Keio University

• Sasaki Hiroshi

  Graduate School of Information Science and Technology, The University of Tokyo

• ZHANG Hao

  Graduate School of Information, Production and System, Waseda University

• TAKE Yasuhiro

  Graduate School of Science and Technology, Keio University

• MATSUTANI Hiroki

  Graduate School of Science and Technology, Keio University

• KURODA Tadahiro

  Graduate School of Science and Technology, Keio University

• ZHANG Hao

  Graduate School of Science and Technology, Keio University

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著作論文

• Evaluation of a multicore reconfigurable architecture (VLSI設計技術)
• Evaluation of a multicore reconfigurable architecture (システムLSI設計技術)
• Evaluation of a multicore reconfigurable architecture (リコンフィギャラブルシステム)
• Evaluation of a multicore reconfigurable architecture (コンピュータシステム)
• A temporal correlation based port combination methodology for application-specific networks-on-chip on FPGAs (計算機アーキテクチャ・2007年並列/分散/協調処理に関する『旭川』サマー・ワークショップ(SWoPP旭川2007)--研究会・連続同時開催)
• Adaptive Data Compression on 3D Network-on-Chips
• Adaptive Data Compression on 3D Network-on-Chips
• Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

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