Adaptive Data Compression on 3D Network-on-Chips
スポンサーリンク
概要
- 論文の詳細を見る
The three-dimensional Network-on-Chip (3D NoC) is an emerging research topic exploring the network architecture of 3D ICs that stack several wafers or dies. As such topics being extensively studied, it is found negative impacts of 3D NoC's vertical interconnects are raising concerns considering their footprint sizes and routability degradation. In our evaluation, we found such vertical bandwidth limitation can dramatically degrade system performance by up to 2.3×. Since such limitations come from physical design constraints, to mitigate performance degradation, we have no other choice but to reduce the amount of communication data on-chip, especially for those data moving vertically. In this paper, therefore, we carry out a study of data compression on 3D NoC architectures with a comprehensive set of scientific workloads. Firstly, we propose an adaptive data compression scheme for 3D NoCs, taking account of the vertical bandwidth limitation and data compressibility. Secondly, we evaluate our proposal on a 3D NoC platform and we observe that the compressibility based adaptive compression is very useful against incompressible data while the location-based adaptive compression is more effective with more layers for the 3D NoC. Thirdly, we find that in a bandwidth limited situation like a CMP with 3D NoCs having multiple connected layers, adaptive data compression with location-based control or with both compressibility and location based control is very promising if the number of layers grows.
著者
-
Nakamura Hiroshi
Graduate School Of Information Science And Technology The University Of Tokyo
-
Matsutani Hiroki
Graduate School of Information Science and Technology, The University of Tokyo
-
He Yuan
Graduate School of Engineering, The University of Tokyo
-
SASAKI Hiroshi
Graduate School of Agricultural and Life Sciences, The University of Tokyo
関連論文
- Evaluation of a multicore reconfigurable architecture (VLSI設計技術)
- Evaluation of a multicore reconfigurable architecture (システムLSI設計技術)
- Evaluation of a multicore reconfigurable architecture (リコンフィギャラブルシステム)
- Evaluation of a multicore reconfigurable architecture (コンピュータシステム)
- A temporal correlation based port combination methodology for application-specific networks-on-chip on FPGAs (計算機アーキテクチャ・2007年並列/分散/協調処理に関する『旭川』サマー・ワークショップ(SWoPP旭川2007)--研究会・連続同時開催)
- Estimating colony locations of bumble bees with moving average model
- Experimental Study on Desalination of Seawater in Imari Bay Using an Upward Spray Flash Desalination Plant
- Crystal structure of monomeric sarcosine oxidase from Bacillus sp. NS-129 reveals multiple conformations at the active-site loop
- Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model
- Adaptive Data Compression on 3D Network-on-Chips
- Adaptive Data Compression on 3D Network-on-Chips
- Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
- Large Volume Coagulation Utilizing Multiple Cavitation Clouds Generated by Array Transducer Driven by 32 Channel Drive Circuits
- Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design
- Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs