Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System (Special Issue on LSI Failure Analysis)
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概要
- 論文の詳細を見る
Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.
- 社団法人電子情報通信学会の論文
- 1994-04-25
著者
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Miura K
Faculty Of Engineering Gunma University
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FUJIOKA Hiromu
Department of Information Systems Engineering, Faculty of Engineering, Osaka University
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Nakamae K
Osaka Univ. Suita‐shi Jpn
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Nakamae Koji
Faculty Of Engineering Osaka University
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Fujioka H
Osaka Univ. Suita‐shi Jpn
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Fujioka Hiromu
Faculty Of Engineering Osaka University
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MIURA Katsuyoshi
Faculty of Engineering, Osaka University
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Nakagaki Ryo
Faculty of Engineering, Osaka University
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Nakagaki Ryo
Faculty Of Engineering Osaka University
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