Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process

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概要

• 論文の詳細を見る

• We evaluate the effect of express lots on production dispatching rule scheduling and cost in VLSI manufacturing final test process. In the assignment of express lots, we make comparisons of two rules, First In First Out (FIFO) rule which is widely used and WEIGHT+RPM rule which considers the time required for jig and temperature exchanges, the remaining processing time of the machine in use and the lot waiting time in queue. When using FIFO rule, the test efficiency begins to deteriorate and the test cost per chip begins to increase, if the content of express lots exceeds 15%. Furthermore, for 30% of express lots' content, the number of total processed lots decreases by 19% and the test cost per chip increases by 22% in comparison to the cases including no express lots. For WEIGHT+RPM rule, however, the test efficiency does not deteriorate and the test cost per chip does not increase even if the content of express lots is increased up to 50%. When we use WEIGHT+RPM rule, Express Lots Tolerances (ELTS), defined as the maximum content of express lots which permits the deterioration of the system characteristics by 5%, are about three times as high as ones when using FIFO rule. It is also found that WEIGHT+RPM rule maintains higher ELTS against the changes in the numbers of planned chips and prepared jigs as compared with FIFO rule.

• 社団法人電子情報通信学会の論文
• 1999-01-25

著者

• FUJIOKA Hiromu

  Department of Information Systems Engineering, Faculty of Engineering, Osaka University

• Nakamae K

  Osaka Univ. Suita‐shi Jpn

• Nakamae Koji

  Faculty Of Engineering Osaka University

• Fujioka H

  Osaka Univ. Suita‐shi Jpn

• Fujioka Hiromu

  Faculty Of Engineering Osaka University

• CHIKAMURA Akihisa

  Faculty of Engineering, Osaka University

• Chikamura Akihisa

  Faculty Of Engineering Osaka University

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