Effect of 300mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
スポンサーリンク
概要
- 論文の詳細を見る
The effect of lot size change and test processing logistics on VLSI manufacturing final test process efficiency and cost due to the transition of from conventional 5 or 6 inches to 300 mm (12 inches) in wafer size is evaluated through simulation analysis. Simulated results show that a high test efficiency and a low test cost are maintained regardless of arrival lot size in the range of the number of 300 mm wafers per lot from 1 to 25 and the content of express lots in the range of up to 50% by using WEIGHT+RPM rule and the right final test processing logistics. WEIGHT+RPM rule is the rule that considers the jig and temperature exchanging time, the lot waiting time in queue and also the remaining processing time of the machine in use. The logistics has a small processing and moving lot size equal to the batch size of testing equipment.
- 社団法人電子情報通信学会の論文
- 1999-04-25
著者
-
FUJIOKA Hiromu
Department of Information Systems Engineering, Faculty of Engineering, Osaka University
-
Nakamae K
Osaka Univ. Suita‐shi Jpn
-
Nakamae Koji
Faculty Of Engineering Osaka University
-
Fujioka H
Osaka Univ. Suita‐shi Jpn
-
Fujioka Hiromu
Faculty Of Engineering Osaka University
-
CHIKAMURA Akihisa
Faculty of Engineering, Osaka University
-
Chikamura Akihisa
Faculty Of Engineering Osaka University
関連論文
- Edge Roughness Study of Chemically Amplified Resist in Low-Energy Electron-Beam Lithography Using Computer Simulation
- Observation of Nuclear Excitation by Electron Transition (NEET) in ^Au with a Nanosecond Stroboscopic Electron Spectrometer
- Three-Dimensional Eye Movement Simulator Extracting Instantaneous Eye Movement Rotation Axes, the Plane Formed by Rotation Axes, and Innervations for Eye Muscles(Medical Engineering)
- EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout(Special Issue on Test and Verification of VLSI)
- Evaluation of Inspection Process Strategies through VLSI Wafer-Process Simulation Analysis
- An Analysis of the Economics of the VLSI Development Including Test Cost
- Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using I_DDQ(Special Section on Reliability Theory and Its Applications)
- Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
- Effect of 300mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
- Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process
- Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System
- Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System
- Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System (Special Issue on LSI Failure Analysis)
- Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System
- Time- and Space-Focusing Detector System for Real-Time Electron Beam Testing
- Measurement of Surface Vacuum Potential from the Energy Spectrum of the Secondary Electron in the Scanning Electron Microscope
- LSI Failure Analysis with CAD-Linked Electron Beam Test System and Its Cost Evaluation (Special Issue on LSI Failure Analysis)
- Efficient Dynamic Fault Imaging by Fully Utilizing CAD Data in CAD-Linked Electron Beam Test System (Special Issue on LSI Failure Analysis)