EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout(Special Issue on Test and Verification of VLSI)
スポンサーリンク
概要
- 論文の詳細を見る
The EB tester line delay fault localization algorithm for combinational circuits is proposed where line delay fault probabilities are utilized to narrow fault candidates down to one efficiently. Probabilities for two main causes of line delay faults, defects of contact/vias along interconnections and crosstalk, are estimated through layout analysis. The algorithm was applied to 8 kinds of ISCAS'85 benchmark circuits to evaluate its performance where the guided probe (GP) diagnosis was used as the reference method. The proposed method can cut the number of probed lines to about 30% in average compared with those for the GP method. The total fault localization time was 31% of the time for the GP method and was 6% less than that of our previous method where the fault list generated in concurrent fault simulation is utilized.
- 社団法人電子情報通信学会の論文
- 2002-10-01
著者
-
Nomura Kazuhiro
Deparmtent of Neurosurgery
-
FUJIOKA Hiromu
Department of Information Systems Engineering, Faculty of Engineering, Osaka University
-
NAKAMAE Koji
Department of Information System Engineering, Graduate School of Information Science and Technology,
-
Nakamae Koji
Department Of Information Systems Engineering Guraduate School Of Information Science And Technology
-
Nakamae Koji
Department Of Electronic Engineering Faculty Of Engineering Osaka University
-
Fujioka Hiromu
Department Of Information Systems Engineering Guraduate School Of Information Science And Technology
-
Fujioka Hiromu
Department Of Electronic Engineering Faculty Of Engineering Osaka University
-
Nomura Kazuhiro
Department Of Information Systems Engineering Guraduate School Of Engineering Osaka University
関連論文
- Statistical Analysis of Chronic Subdural Hematoma in 309 adult Cases
- Induced Cholesteric Liquid Crystalline Polymers
- Thermal Properties of Side Chain Type Liquid Crystalline Copolymer Composed of a Mesogenic Monomer and Non-Mesogenic Chiral Monomer
- Edge Roughness Study of Chemically Amplified Resist in Low-Energy Electron-Beam Lithography Using Computer Simulation
- New Approach of Laser-SQUID Microscopy to LSI Failure Analysis
- Isochronous Detector for Real-Time Electron Beam Testing : Inspection and Testing
- Observation of Nuclear Excitation by Electron Transition (NEET) in ^Au with a Nanosecond Stroboscopic Electron Spectrometer
- A-69. Cell Kinetic Changes of Malignant Glioma Cells Treated with DBcAMP
- B-9. The Effect of (But)_2cAMP on the Malignant Glioma Calls : from the View Point of Cell Kinetics
- Three-Dimensional Eye Movement Simulator Extracting Instantaneous Eye Movement Rotation Axes, the Plane Formed by Rotation Axes, and Innervations for Eye Muscles(Medical Engineering)
- EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout(Special Issue on Test and Verification of VLSI)
- Evaluation of Inspection Process Strategies through VLSI Wafer-Process Simulation Analysis
- C-12-5 Methodology for Layout-Based Diagnosis of VLSI Chips Considering Temperature Distribution
- Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using I_DDQ(Special Section on Reliability Theory and Its Applications)
- Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
- Effect of 300mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
- Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process
- Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System
- Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System
- Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System (Special Issue on LSI Failure Analysis)
- Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System
- Time- and Space-Focusing Detector System for Real-Time Electron Beam Testing
- Measurement of Surface Vacuum Potential from the Energy Spectrum of the Secondary Electron in the Scanning Electron Microscope
- A New CD Measurement Method Linked with the Electrical Properties of Devices
- Immobilization of Photosynthetic Reaction Center Complexes onto a Hydroquinonethiol-Modified Gold Electrode
- 光合成反応中心懸濁液中に浸漬したヒドロキノンチオ-ル修飾金電極上での光アノ-ド電流の発生
- Post-Treatment Kinetics of BCNU in a 9L Rat Brain Tumor Model
- Present status of brain tumor statistics in Japan
- STATISTICS OF BRAIN TUMORS, 1969-1987 : GENERAL FEATURES