Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System
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概要
- 論文の詳細を見る
An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.
- 社団法人電子情報通信学会の論文
- 1995-11-25
著者
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Miura K
Faculty Of Engineering Gunma University
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FUJIOKA Hiromu
Department of Information Systems Engineering, Faculty of Engineering, Osaka University
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Nakamae K
Osaka Univ. Suita‐shi Jpn
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Nakamae Koji
Faculty Of Engineering Osaka University
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Fujioka H
Osaka Univ. Suita‐shi Jpn
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Fujioka Hiromu
Faculty Of Engineering Osaka University
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MIURA Katsuyoshi
Faculty of Engineering, Osaka University
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