Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System

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概要

• 論文の詳細を見る

• An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.

• 社団法人電子情報通信学会の論文
• 1994-03-25

著者

• Miura K

  Faculty Of Engineering Gunma University

• FUJIOKA Hiromu

  Department of Information Systems Engineering, Faculty of Engineering, Osaka University

• Nakamae K

  Osaka Univ. Suita‐shi Jpn

• Nakamae Koji

  Faculty Of Engineering Osaka University

• Fujioka H

  Osaka Univ. Suita‐shi Jpn

• Fujioka Hiromu

  Faculty Of Engineering Osaka University

• MIURA Katsuyoshi

  Faculty of Engineering, Osaka University

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