Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using I_DDQ(Special Section on Reliability Theory and Its Applications)

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概要

• 論文の詳細を見る

• Abnormal I_DDQ(Quiescent V_DD supply current)indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal I_DDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal I_DDQ exists in normal logic state or not.

• 社団法人電子情報通信学会の論文
• 2000-05-25

著者

• FUJIOKA Hiromu

  Department of Information Systems Engineering, Faculty of Engineering, Osaka University

• Fujioka H

  Osaka Univ. Suita‐shi Jpn

• Fujioka Hiromu

  Department Of Electronic Engineering Faculty Of Engineering Osaka University

• SANADA Masaru

  Device Analysis Technology Laboratories, NEC Co.

• Sanada Masaru

  Device Analysis Technology Laboratories Nec Co.:department Of Information Systems Engineering Facult

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