Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
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概要
- 論文の詳細を見る
Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.
- 社団法人電子情報通信学会の論文
- 1999-06-25
著者
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FUJIOKA Hiromu
Department of Information Systems Engineering, Faculty of Engineering, Osaka University
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Nakamae K
Osaka Univ. Suita‐shi Jpn
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Fujioka H
Osaka Univ. Suita‐shi Jpn
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CHIKAMURA Akihisa
the Faculty of Engineering, Osaka University
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NAKAMAE Koji
the Faculty of Engineering, Osaka University
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FUJIOKA Hiromu
the Faculty of Engineering, Osaka University
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CHIKAMURA Akihisa
Faculty of Engineering, Osaka University
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Chikamura Akihisa
Faculty Of Engineering Osaka University
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