A New CD Measurement Method Linked with the Electrical Properties of Devices
スポンサーリンク
概要
- 論文の詳細を見る
This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively.
- 社団法人電子情報通信学会の論文
- 1999-07-25
著者
-
Fujioka Hiromu
Department Of Information Systents Engineering Faculty Of Engineering Osaka University
-
Fujioka Hiromu
Department Of Electronic Engineering Faculty Of Engineering Osaka University
-
Miyoshi Motosuke
Integrated Circuit Advanced Process Technology Department Toshiba Corp.
-
KOMATSU Fumio
Integrated Circuit Advanced Process Technology Department, Toshiba Corp.
-
Komatsu Fumio
Integrated Circuit Advanced Process Technology Department Toshiba Corp.
関連論文
- Edge Roughness Study of Chemically Amplified Resist in Low-Energy Electron-Beam Lithography Using Computer Simulation
- Observation of Nuclear Excitation by Electron Transition (NEET) in ^Au with a Nanosecond Stroboscopic Electron Spectrometer
- Three-Dimensional Eye Movement Simulator Extracting Instantaneous Eye Movement Rotation Axes, the Plane Formed by Rotation Axes, and Innervations for Eye Muscles(Medical Engineering)
- EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout(Special Issue on Test and Verification of VLSI)
- Evaluation of Inspection Process Strategies through VLSI Wafer-Process Simulation Analysis
- Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using I_DDQ(Special Section on Reliability Theory and Its Applications)
- Time- and Space-Focusing Detector System for Real-Time Electron Beam Testing
- Measurement of Surface Vacuum Potential from the Energy Spectrum of the Secondary Electron in the Scanning Electron Microscope
- A New CD Measurement Method Linked with the Electrical Properties of Devices