MIURA Katsuyoshi | Faculty of Engineering, Osaka University
スポンサーリンク
概要
関連著者
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Miura K
Faculty Of Engineering Gunma University
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FUJIOKA Hiromu
Department of Information Systems Engineering, Faculty of Engineering, Osaka University
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Nakamae K
Osaka Univ. Suita‐shi Jpn
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Nakamae Koji
Faculty Of Engineering Osaka University
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Fujioka H
Osaka Univ. Suita‐shi Jpn
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Fujioka Hiromu
Faculty Of Engineering Osaka University
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MIURA Katsuyoshi
Faculty of Engineering, Osaka University
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Nakagaki Ryo
Faculty of Engineering, Osaka University
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Nakagaki Ryo
Faculty Of Engineering Osaka University
著作論文
- Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System
- Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System
- Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System (Special Issue on LSI Failure Analysis)
- Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System