A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation(Integrated Electronics)
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概要
- 論文の詳細を見る
A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stubseries terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF × 4 stub load. Active chip area and power consumption are 300 × 1000 μm^2 and 142 mW, respectively, with a 2.5 V, 0.25 μm CMOS process.
- 社団法人電子情報通信学会の論文
- 2004-05-01
著者
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Cho S‐i
Dram Design Samsung Electronics Company
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Park H‐j
Pohang Univ. Sci. And Technol. Kyungbuk Kor
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Park Hong-june
Vlsi Systems Laboratory Pohang University Of Science And Technology (postech)
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Park H‐j
Pohang Univ. Sci. And Technol. (postech) Kor
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Cho Seong-ik
Hynix Semiconductor
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Cho Soo-in
Product Development Center Memory Division Samsung Electronics
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Cho Soo-in
Dram Design Samsung Electronics Company
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Park Hong-june
Department Of Electrical Engineering Pohang University Of Science And Technology
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SOHN Young-Soo
Department of Electrical Engineering, Pohang University of Science and Technology
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BAE Seung-Jun
Department of Electrical Engineering, Pohang University of Science and Technology
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Bae Seung-jun
Department Of Electrical Engineering Pohang University Of Science And Technology
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Sohn Young-soo
Department Of Electrical Engineering Pohang University Of Science And Technology
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Sohn Young-soo
Physics Department Hanyang University
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