A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive
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概要
- 論文の詳細を見る
A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.
- 社団法人電子情報通信学会の論文
- 1999-09-25
著者
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Lee Sang-hoon
Vlsi Systems Laboratory Pohang University Of Science And Technology (postech)
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Kim Jin-cheon
Vlsi Systems Laboratory Pohang University Of Science And Technology (postech)
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PARK Hong-June
VLSI Systems Laboratory, Pohang University of Science and Technology (POSTECH)
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Lee S‐h
Electronics And Telecommunications Res. Inst. (etri) Daejeon Kor
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Park H‐j
Pohang Univ. Sci. And Technol. Kyungbuk Kor
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Park Hong-june
Vlsi Systems Laboratory Pohang University Of Science And Technology (postech)
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Park H‐j
Pohang Univ. Sci. And Technol. (postech) Kor
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Park Hong-june
Department Of Electrical Engineering Pohang University Of Science And Technology
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