An 8-Bit 200MS/s CMOS Folding/Interpolating Analog-to-Digital Converter
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概要
- 論文の詳細を見る
An 8-bit 200MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35μm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2ns to 1.3ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.
- 社団法人電子情報通信学会の論文
- 2003-04-01
著者
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Park S‐h
Tokyo Inst. Technol. Tokyo Jpn
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Park H‐j
Pohang Univ. Sci. And Technol. Kyungbuk Kor
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Park Hong-june
Vlsi Systems Laboratory Pohang University Of Science And Technology (postech)
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Jang Young-chan
Samsung Electronics
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Park Hong‐june
Pohang University Of Science And Technology (postech)
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Park H‐j
Pohang Univ. Sci. And Technol. (postech) Kor
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PARK Sang-Hune
Pohang University of Science and Technology (POSTECH)
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Park Hong-june
Department Of Electrical Engineering Pohang University Of Science And Technology
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Park Sang‐hune
Pohang University Of Science And Technology (postech)
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Heo Seung-chan
Rf Design Project System Lsi Samsung Electronics Company
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HEO Seung-Chan
The authors are with High-Speed CMOS IC Lab., Department of Electrical Engineering. Pohang Universit
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JANG Young
The authors are with High-Speed CMOS IC Lab., Department of Electrical Engineering. Pohang Universit
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PARK Sang-Hune
The authors are with High-Speed CMOS IC Lab., Department of Electrical Engineering. Pohang Universit
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PARK Hong-June
The authors are with High-Speed CMOS IC Lab., Department of Electrical Engineering. Pohang Universit
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Park Se-hyun
Department Of Electrical And Electronic Tokyo Institute Of Technology
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