An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator(<Special Section>Analog Circuits and Related SoC Integration Technologies)
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概要
- 論文の詳細を見る
An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-μm CMOS process. Eight uniformly-spaced 1.1GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0bits was measured to be 1.2GHz. The chip area and power consumption were 2.24mm^2 and 1.6W, respectively.
- 社団法人電子情報通信学会の論文
- 2007-06-01
著者
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SIM Jae-Yoon
Pohang University of Science and Technology (POSTECH)
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PARK Hong
Pohang University of Science and Technology (POSTECH)
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Park S‐h
Tokyo Inst. Technol. Tokyo Jpn
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Park Hong-june
Pohang University Of Science And Technology (postech)
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Jang Young-chan
Samsung Electronics
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Sim Jae‐yoon
Pohang University Of Science And Technology (postech)
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Park Hong‐june
Pohang University Of Science And Technology (postech)
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BAE Jun-Hyun
Pohang University of Science and Technology (POSTECH)
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PARK Sang-Hune
Pohang University of Science and Technology (POSTECH)
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Park Sang‐hune
Pohang University Of Science And Technology (postech)
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Park Se-hyun
Department Of Electrical And Electronic Tokyo Institute Of Technology
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