An 8-GS/s 4-Bit 340 mW CMOS Time Interleaved Flash Analog-to-Digital Converter(<Special Section>Analog Circuit Techniques and Related Topics)
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概要
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An 8-GS/s 4-bit CMOS analog-to-digital converter (ADC) chip was implemented by using a time interleaved flash architecture for very high frequency mixed signal applications with a 0. 18-μm single-poly five-metal CMOS process. Eight 1-GS/s flash ADCs were time-interleaved to achieve the 8-GHz sampling rate. Eight uniformly-spaced 1 GHz clocks were generated by using a phase-locked-loop (PLL) with the peak-to-peak and rms jitters of 29.6 ps and 3.78 ps respectively. An input buffer including a preamplifier array (fifteen preamplifiers, four dummy amplifiers and averaging resistors) was shared among eight 1-GS/s flash ADCs to reduce the input capacitance and the mismatches among eight 1-GS/s flash ADCs. The adjacent output nodes of preamplifiers were connected by a resistor (resistor-averaging) to reduce the effects of the input offset voltage and the load mismatches of preamplifiers. A source follower circuit was added at the output node of a preamplifier to drive eight distributed track and hold (DTK) circuits. The Input bandwidth ofADC was measured to be 2.5 GHz. The measured SFDR values at the sampling rate of 8-GS/s were 25 dB and 22 dB for the 1.033 GHz and 2.5 GHz sinusoidal input signals respectively. The power consumption and the active input voltage range were 340 mW and 700 mV peak-to-peak, respectively, at the sampling rate of 8-GS/s and the supply voltage of 1.8 V. The active chip area was 1.32mm^2.
- 社団法人電子情報通信学会の論文
- 2004-02-01
著者
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Park S‐h
Tokyo Inst. Technol. Tokyo Jpn
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Park H‐j
Pohang Univ. Sci. And Technol. Kyungbuk Kor
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Park Hong-june
Vlsi Systems Laboratory Pohang University Of Science And Technology (postech)
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Jang Young-chan
Samsung Electronics
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Park Hong‐june
Pohang University Of Science And Technology (postech)
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Park H‐j
Pohang Univ. Sci. And Technol. (postech) Kor
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PARK Sang-Hune
Pohang University of Science and Technology (POSTECH)
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Park Hong-june
Department Of Electrical Engineering Pohang University Of Science And Technology
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PARK Hong-June
IC Laboratory, Pohang University of Science and Technology(POSTECH)
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Park Sang‐hune
Pohang University Of Science And Technology (postech)
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Heo Seung-chan
Rf Design Project System Lsi Samsung Electronics Company
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JANG Young-Chan
IC Lab., Department of Electronic Engineering, Pohang University of Science and Technology (POSTECH)
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PARK Sang-Hune
IC Lab., Department of Electronic Engineering, Pohang University of Science and Technology (POSTECH)
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Park Se-hyun
Department Of Electrical And Electronic Tokyo Institute Of Technology
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PARK Hong-June
IC Lab., Department of Electronic Engineering, Pohang University of Science and Technology (POSTECH)
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