An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation
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概要
- 論文の詳細を見る
This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6GHz.
- （社）電子情報通信学会の論文
- 2010-12-01
著者
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SIM Jae-Yoon
Pohang University of Science and Technology (POSTECH)
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PARK Hong
Pohang University of Science and Technology (POSTECH)
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Park Hong-june
Pohang University Of Science And Technology (postech)
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Sim Jae‐yoon
Pohang University Of Science And Technology (postech)
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Park Hong‐june
Pohang University Of Science And Technology (postech)
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KIM Young-Sang
Pohang University of Science and Technology (POSTECH)
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SUH Yunjae
Pohang University of Science and Technology (POSTECH)
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