CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin(Integrated Electronics)

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概要

• 論文の詳細を見る

• A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• Cho S‐i

  Dram Design Samsung Electronics Company

• Kim Y‐h

  Changwon National Univ. Changwon‐si Kor

• Park Hong-june

  Pohang University Of Science And Technology (postech)

• Kim Young-hee

  Vlsi Design Laboratory Changwon National University

• Kim Young-hee

  Changwon National University

• Cho Seong-ik

  Hynix Semiconductor

• Cho Soo-in

  Product Development Center Memory Division Samsung Electronics

• Heo Jin-seok

  Changwon National University

• Park Mu-hun

  Changwon National University

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