Cho S‐i | Dram Design Samsung Electronics Company

スポンサーリンク

概要

関連著者

もっと見る

著作論文

16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Variable V_<CC> Design Techniques for Battery-Operated DRAM's (Special Section on the 1992 VLSI Circuits Symposium)
A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation(Integrated Electronics)
An Analytic Time Jitter Equation of NRZ Signals in Uniformly Loaded PCB Transmission Lines
CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin(Integrated Electronics)
A Paired MOS Charge Pump for Low Voltage Operation(Electronic Circuits)

スポンサーリンク