A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System
スポンサーリンク
概要
- 論文の詳細を見る
Recent advanced technology makes digital circuits small and the number of digital functional blocks that can be integrated on a single chip is increasing rapidly. On the other hand, reduction in the size of analog circuits has been insufficient. This means that the analog circuit area is relatively large, and reducing analog circuit area can be effective to make a low cost radio receiver. In this paper, a new wireless receiver architecture that occupies small analog area is proposed, and measured results of the core analog blocks are described. To reduce the analog area, a balanced 3-phase analog system is adopted and the functions of analog baseband filters and VGAs are moved to the digital domain. The test chip consists of a 3-phase downconverter and a 3-phase ADC. There is no analog baseband filter on the chip and the analog filter is assumed to be replaced with a digital filter. The downconverter and ADC occupy 0.28mm2. The measured results show the possibility that the requirements for IMT-2000 are fulfilled even with a small chip area.
- 2010-02-01
著者
-
ITAKURA Tetsuro
Corporate Research & Development Center, Toshiba Corporation
-
Itakura Tetsuro
Toshiba Corp. Kawasaki‐shi Jpn
-
Ueno Takeshi
Corporate Research And Development Center Toshiba Corporation
-
YAMAJI Takafumi
Corporate Research and Development Center, Toshiba Corporation
-
Ueno Takeshi
Corporate Research & Development Center Toshiba Corporation
-
Yamaji Takafumi
Corporate Research And Development Center Toshiba Corporation
-
Yamaji Takafumi
Corporate Research & Development Center Toshiba Corp.
関連論文
- A Fast f_c Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems(Analog Circuits and Related SoC Integration Technologies)
- A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA(RF, Analog Circuit and Device Technologies)
- Phase Compensation Technique for a Low-Power Transconductor(Building Block, Analog Circuit and Device Technologies)
- Phase Compensation Techniques for Low-Power Operational Amplifiers
- A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter
- 1.9 GHz Si Direct Conversion Receiver IC for QPSK Modulation Systems (Special Issue on Microwave Devices for Mobile Communications)
- A 1.2-V, 12-bit, 200MSample/s Current-Steering D/A Converter in 90-nm CMOS(Analog Circuit Techniques and Related Topics)
- A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals
- A 2-V_ Linear Input-Range Fully Balanced CMOS Transconductor and Its Application to a 2.5-V 2.5-MHz Gm-C LPF
- Low Output Offset,8-bit Signal Driver ICs for XGA/SVGA TFT-LCDs (特集高性能アナログ電子回路)
- A Simple Modeling Technique for Symmetric Inductors(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System
- 55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
- 1.2V, 24mW/ch, 10bit, 80MSample/s Pipelined A/D Converters
- Low-Power Design of 10-bit 80-MSPS Pipeline ADCs(Analog Signal Processing)
- A 0.9V 1.5mW Continuous-Time ΔΣ Modulator for W-CDMA(Analog Circuit Techniques and Related Topics)
- Nonlinear Analysis of Bipolar Harmonic Mixer for Direct Conversion Receivers(RF, Analog Circuit and Device Technologies)
- A Two-Gain-Stage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC
- A 380-MHz CMOS Linear-in-dB Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems
- A Gm-C Filter Using Multiple-Output Linearized Transconductors(Analog Circuit Techniques and Related Topics)
- A 380-MHz CMOS Linear-in-dB Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer(Special Section on Analog Circuit Techniques and Related Topics)
- A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS