A 0.9V 1.5mW Continuous-Time ΔΣ Modulator for W-CDMA(<Special Section>Analog Circuit Techniques and Related Topics)
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概要
- 論文の詳細を見る
This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-μm CMOS technology. It consumes only 1.5mW. The measured SNDR is 50.9dB over a bandwidth of 1.92MHz.
- 社団法人電子情報通信学会の論文
- 2005-02-01
著者
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ITAKURA Tetsuro
Corporate Research & Development Center, Toshiba Corporation
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Ueno Takeshi
Corporate Research & Development Center Toshiba Corporation
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