A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS
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概要
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This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14mm2 and the ADC consumes 36mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4dB and 39.6dB, respectively, and an figure of Merit (FoM) of 300fJ/conv. is achieved.
著者
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ITAKURA Tetsuro
Corporate Research & Development Center, Toshiba Corporation
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FURUTA Masanori
Corporate Research and Development Center, Toshiba Corporation
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AKITA Ippei
Department of Electrical & Electronic Information Engineering, Toyohashi University of Technology
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MATSUNO Junya
Corporate Research and Development Center, Toshiba Corporation
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- A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS