A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer(<特集>Special Section on Analog Circuit Techniques and Related Topics)
スポンサーリンク
概要
- 論文の詳細を見る
A 2-GHz down-converter for wide-band wireless communication systems is described. To achieve both wide-band output characteristic and LO signal suppression, an on-chip LC series resonator which is resonated at LO signal frequency and a transimpedance amplifier which is used in the output buffer circuit are used. To achieve a low sensitivity to temperature, two kinds of bias circuits; a V_T reference current source and a bandgap reference current source are used. The measured 3-dB bandwidth of 600 MHz is achieved. The conversion gain varies less than 0.2dB within 200 MHz ± 10MHz and 400 MHz ± 10MHz band and 0.7dB for the temperature range from -34℃ to 850℃. At room temperature, conversion gain of 15dB, NF of 9.5dB and IIP3 of -5dBm are obtained respectively. The down-converter is fabricated using Si BiCMOS process with f_t=20 GHz, and it occupies approximately 1 mm^2.
- 社団法人電子情報通信学会の論文
- 2002-02-01
著者
-
WATANABE Osamu
Corporate Research & Development Center, Toshiba Corporation
-
ITAKURA Tetsuro
Corporate Research & Development Center, Toshiba Corporation
-
Itakura Tetsuro
Corporate Research & Development Center Toshiba Corp.
-
Hattori Ichiro
Toshiba Corporation Semiconductor Company
-
Yamaji Takafumi
Corporate Research & Development Center Toshiba Corp.
-
Watanabe Osamu
Corporate Research & Development Center Toshiba Corp.
関連論文
- A Fast f_c Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems(Analog Circuits and Related SoC Integration Technologies)
- A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA(RF, Analog Circuit and Device Technologies)
- Phase Compensation Technique for a Low-Power Transconductor(Building Block, Analog Circuit and Device Technologies)
- Phase Compensation Techniques for Low-Power Operational Amplifiers
- A 1.2-V, 12-bit, 200MSample/s Current-Steering D/A Converter in 90-nm CMOS(Analog Circuit Techniques and Related Topics)
- A Triple-Band WCDMA Direct Conversion Receiver IC with Reduced Number of Off-Chip Components and Digital Baseband Control Signals
- A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals
- A 2-V_ Linear Input-Range Fully Balanced CMOS Transconductor and Its Application to a 2.5-V 2.5-MHz Gm-C LPF
- A Simple Modeling Technique for Symmetric Inductors(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage(Analog Circuits and Related SoC Integration Technologies)
- A Low LO Leakage and Low Power LO Buffer for Direct-Conversion Quadrature Demodulator(RF, Analog Circuit and Device Technologies)
- A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System
- 1.2V, 24mW/ch, 10bit, 80MSample/s Pipelined A/D Converters
- A 0.9V 1.5mW Continuous-Time ΔΣ Modulator for W-CDMA(Analog Circuit Techniques and Related Topics)
- Nonlinear Analysis of Bipolar Harmonic Mixer for Direct Conversion Receivers(RF, Analog Circuit and Device Technologies)
- A Two-Gain-Stage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC
- A 380-MHz CMOS Linear-in-dB Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems
- A Gm-C Filter Using Multiple-Output Linearized Transconductors(Analog Circuit Techniques and Related Topics)
- A 380-MHz CMOS Linear-in-dB Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer(Special Section on Analog Circuit Techniques and Related Topics)
- A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS