1.2V, 24mW/ch, 10bit, 80MSample/s Pipelined A/D Converters
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概要
- 論文の詳細を見る
This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24mW/ch from a 1.2V power supply. The measured SNR and SNDR are 58.6dB and 52.2dB, respectively.
- （社）電子情報通信学会の論文
- 2008-02-01
著者
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ITAKURA Tetsuro
Corporate Research & Development Center, Toshiba Corporation
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Itakura Tetsuro
Toshiba Corp. Kawasaki‐shi Jpn
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Ueno Takeshi
Corporate Research And Development Center Toshiba Corporation
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Ito Tomohiko
Toshiba Corp. Kawasaki‐shi Jpn
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YAMAJI Takafumi
Corporate Research and Development Center, Toshiba Corporation
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ITO Tomohiko
Corporate Research & Development Center, Toshiba Corporation
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KUROSE Daisuke
Corporate Research & Development Center, Toshiba Corporation
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Ueno Takeshi
Corporate Research & Development Center Toshiba Corporation
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Yamaji Takafumi
Corporate Research And Development Center Toshiba Corporation
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Yamaji Takafumi
Corporate Research & Development Center Toshiba Corp.
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